library verilog;
use verilog.vl_types.all;
entity Adder_8bits is
    port(
        LEDR            : out    vl_logic_vector(7 downto 0);
        LEDG            : out    vl_logic_vector(1 downto 0);
        A               : in     vl_logic_vector(7 downto 0);
        B               : in     vl_logic_vector(7 downto 0);
        c_in            : in     vl_logic
    );
end Adder_8bits;
